1. Field of the Invention
The present invention relates to a data transfer apparatus and a data transfer method, and more particularly to a data transfer apparatus and a data transfer method that guarantee completion of writing of transferred data to a memory.
2. Description of the Related Art
Technology that transfers data directly between a memory and various devices utilizing a data transfer method such as direct memory access (hereunder, referred to as “DMA”) is already in widespread use in various kinds of electronic equipment such as personal computers. A data transfer method such as DMA is a method that transfers data by bypassing a processor such as a central processing unit (hereunder, referred to as “CPU”).
For example, in DMA transfer processing, although the transfer of data is performed by bypassing the CPU, there is a problem that the load of the CPU with respect to settings processing for a DMA controller (hereunder, referred to as “DMAC”) and the like increases. To solve this problem, technology has been disclosed in which, when a CPU instructs a DMAC to execute data transfer processing, after transferring the data and completing the data transfer operation, the DMAC sets a completion status that indicates completion of the data transfer in a status register (for example, see Japanese Patent Laid-Open No. 2005-78596).
According to the aforementioned technology, by monitoring whether or not a completion status is written after instructing the DMAC to execute data transfer processing, the CPU can recognize that the data transfer processing is completed and execute processing in accordance with that completion.
However, in the technology relating to that disclosure, there is the problem that since the CPU must constantly monitor whether or not the completion status is written after issuing a data transfer instruction to the DMAC, the overheads for that monitoring are large.
Further, in recent years computer architecture having a plurality of buses, such as PC architecture having a so-called “Northbridge” and “Southbridge”, has also been brought into practical use.
For example, in systems having a processor, a companion chip, and a system memory, there are cases in which mutual accesses are performed through a plurality of buses. Therefore, for example, even when three types of processing consisting of an access to the system memory from a DMA controller inside the companion chip, an interrupt notification to the processor from a DMA controller inside the companion chip, and an access to the system memory from the processor are started in that order, in some cases the order of the actual access processing between the three components is not guaranteed.
Accordingly, normally after a DMA controller inside a companion chip performs an operation to transfer data to the system memory, the DMA controller sends an interrupt to the processor to notify the processor that the data transfer is completed. Thereafter, the processor detects the interrupt and accesses the system memory to read the transfer data. However, in this kind of system, since each access extends over a plurality of buses, a time lag arises between the time the DMA controller executes the operation to transfer data to the system memory and the time that transfer of the data to the system memory is actually completed, and there is the possibility that the processor may attempt to read the data before the data is actually transferred to the system memory.
In this kind of system, even if the system applies the technology according to the above described disclosure, a similar problem can arise.